Yield analysis is the science and art of predicting and reducing the failure rate of electronic semiconductor devices. Semiconductor devices can fail for many reasons. Identifying the causes of failures is an important initial step in modifying manufacturing process steps to reduce the number of failures to an acceptable level. Many failures can be traced to defects in metallization and/or dielectric layers leading to electrical shorts or opens. An electrical short is an electrical connection between two metal lines that should be electrically isolated from one another. An electrical open is a failure of a metal line to electrically connect its two endpoints. Electrical shorts and electrical opens can be caused by such things as contaminant particles, blocked etch, residue, scratches, etc. at various stages of wafer processing.
FIG. 1 shows an exemplary prior art test structure 50 for identifying the presence of a process defect leading to a short circuit in the structure. Test structure 50 has two comb-shaped conductors 54, 58 interleaved with one another so that a plurality of fingers 55 from first comb-shaped conductor 54 are each positioned between two fingers 59 from second comb-shaped conductor 58. Each finger 55 is permanently electrically connected to every other finger 55 by a busbar 53 so that all fingers 55 are at the same electrical potential. Likewise, all fingers 59 are permanently electrically connected to each other by a busbar 57. Cross-hatching of comb-shaped conductor 54 represents that comb-shaped conductor 54 can be held at a different electrical potential than combshaped conductor 58. Test structure 50 can be manufactured on a substrate, such as a silicon wafer, in a manner consistent with a proposed device to be produced. Therefore a failure rate per unit of critical area will be consistent with an actual electronic device. The purpose of the test structure is to detect defects leading to electrical shorts. A different test structure (not shown) may be used to detect defects leading to electrical opens. Test structure 50 is depicts an exemplary test structure for the purpose of illustration only, and is therefore not to scale. In order to calculate a failure rate corresponding to the critical area of the test structure, an actual test structure may be designed to fill an area that is large enough to capture a defect sometimes but not always. A test structure that is too large may be overly sensitive and therefore nearly always be defective, whereas a test structure that is too small may only rarely capture a defect so that the defect can be identified.
The critical area of a device or a test structure is a well-known concept. The critical area can be calculated mathematically from the geometry of the device using the formula A=∫A(X)f(x)dx, where A(x) is the critical area for particle size having the diameter x, f(x) is the probability that a particle of diameter x will occur, and A is the total critical area. For a short circuit, for example, A(x) is the area over which the center of a particle of diameter x must fall where the particle can touch two adjacent conductors and cause a short. The product of A(x) and f(x) is integrated to determine a total critical area A.
The test structure, like all metallization layers in semiconductor device, may be built in stages. Any suitable process may be used to produce the test structure, such as a damascene or a subtractive process. At any point during process, a defect can occur. For example, a contaminating particle may become embedded in the metallization layer, the etching step may fail to remove a layer of metal, or a scratch can occur in the photomask that determines areas of exposure of the photoresist, causing an incorrect etching. In any case, if a defect occurs that results in a short, the presence of the defect is easily determined by testing for electrical continuity. Electrical continuity can be tested by applying a voltage differential across first and second electrodes 52, 56 and testing for the flow of current. FIG. 2 shows test structure 50 of FIG. 1 having an electricity conducting particle or other defect 60 touching both comb-shaped conductors. As a result of defect 60, the current will flow from the first electrode, through defect 60 causing the short, and then to second electrode 56. If no defect exists, then first and second electrodes will be electrically isolated from one another as in FIG. 1 and current will not flow.
The failure rate of the test structure can be determined by producing a number of test structures and electrically testing each one for electrical continuity. This failure rate can be translated into a failure rate per unit of critical area, also referred to as the electrical defect density. The percentage of failing test structures will be one component in determining the overall relation between critical area, electrical defect density, and yield. Once this relation is determined for a test structure, then by substituting the critical area of a real device for the critical area of the test structure, an accurate prediction can be made as to the yield of a real electronic device. Although such a yield prediction is an important step in identifying the expected cost of production of a device, it provides no information on the primary causes of failures, and what process modifications might be made to reduce the failure rate and thus improve the yield. In order to identify the cause of the defect, it is necessary to view the defect, e.g., using a scanning electron microscope and other known operations. Failure analysis techniques, for example, focused ion beam (FIB) milling may be used to cross-section the area of the defect if the defect is not directly visible. Finally, in order to view the defect, it must first be localized. The term, “localize” means to reduce potential locations of the defect thereby minimizing the time and expense required to identify it. For example, if half the area of test structure 50 can be eliminated as potential positions of the defect, then the defect can be said to have been localized to the area of the remaining half.
Although the presence of an electrical defect is easily determined using electrical testing as described above with reference to FIGS. 1 and 2, its location is not. It should be recognized that the metallization features may be sized on the order of tens of nanometers, and the size of the test structure may be on the order of perhaps tens of square millimeters, in which case the relative surface area over which the defect can occur as compared to the size of the defect is enormous. While visualization tools are commercially available to assist process engineers to visualize and identify individual defects, even these tools can fail to identify a defect that is not visible because, for example, it is buried beneath the metallization layer.
Milling an entire test structure to find a buried defect is too slow and expensive to be feasible. Prior art techniques for identifying non-visible defects resulting in electrical shorts include the use of infra-red imaging. In this technique, the test structure is imaged using an infrared imaging device while passing electricity through the test structure in hopes that the defect will “light up” as a result of heat generated by the electrical current. This technique, however, only works when the short is electrically resistive, which is not always the case, particularly if the short is caused by errant metallization or metal particle.
In another known technique, voltage contrast visualization is used to localize electrical opens and resistive failures. In voltage contrast, an electronic device or test structure is imaged using a scanning electron microscope (SEM). Electricity is input into the electronic device or test structure thereby placing some electronic pathways at a higher voltage potential than other electronic pathways. Because electrons directed at the device by the SEM will respond differently depending on the voltage potential of the conductor, the SEM will image the conductors differently. Generally, the conductors at the lower potential will appear brighter, thus producing “voltage contrast” in the resulting image. There are various techniques for inputting energy in the form of a voltage differential, including, for example, the use of in-situ electrodes for applying the voltage differential during the electron scanning and imaging. When an electrical pathway is open, the charged portion of the line will appear brighter or darker than the uncharged portion, thereby easily identifying the location of the defect as the position where the brightness of the conductor changes. Likewise, a resistive defect can generate a voltage contrast. However, voltage contrast techniques have not heretofore been useful to localize the position of a conductive short since it places the two conductors at the same potential, as represented in FIG. 2 by cross-hatching.
A test structure or method for localizing electrical shorts is needed to reduce the time and expense required to identify the causes of electrical shorts.